Electronic parallel adder/subtractor in BCD 8421 code

摘要

The parallel adder/subtractor according to the subject-matter of the invention is only provided with one binary tetrad adder/subtractor 1 each per decade, which can be switched from addition to subtraction and can be switched from subtraction to addition. Thus, an additional cycle is also required for subtracting the correction number 6 (LHHL) in this parallel adder/subtractor, and not only in the case of an addition for the temporary increase of the sum by the number 6 (LHHL) by adding the number 6 (LHHL). If the additions are connected through according to Figure 4 or 6 or 7, they thus occur in a three-stage switching-through cycle. If the subtractions are connected through in accordance with Figure 5 or 8 or 9, they occur in accordance with a two-stage switching-through cycle. The result numbers thus occur in BCD-0 code both during addition and during subtraction. All numbers are thus input BCD-0 coded and all result numbers occur BCD-0 coded. During the addition, the correction number 6 is subtracted additively by adding the number 10 (HLHL) without processing the relevant carries. <IMAGE>