Apparatus and method for direct memory to peripheral and peripheral to memory data transfer.

摘要

A multi-microprocessor implemented data processing system (10) having a single cycle data transfer capability for its memory mapped peripheral devices (16) is described. A host of controlling microprocessor (12, 14) provides address and control signals for memory (24) accesses. In addition, it also determines that a peripheral (16) operation is desired. When this occurs, a command is sent to the selected peripheral and a memory cycle, fetch or store, for the data transfer is initiated. The address bus is provided with the memory address for the needed data and a special decode that indicates the unique nature of this memory access. Logic circuit means (28) are provided to detect the special decode and to intercept the data bus (22) at the appropriate point in the bus cycle in response thereto. The logic circuit means is adapted to then responsively apply the correct control signals to the peripheral (16) to enable the desired data transfer after the data bus has been intercepted.