发明名称 |
CONTROL CIRCUIT OF BUFFER MEMORY |
摘要 |
PURPOSE:To simplify a circuit by switching two buffer memories by a changeover switch and forming a write end signal on the data writing side in addition to a data writing clock. CONSTITUTION:Each of memories M-1, M-2 is constituted of an input register, a RAM and an output register and data is written in the RAM through the input register at the writing time and outputted from the RAM through the output register. When a write end signal is applied to a terminal (c) after ending the writing, a dummy clock is generated and the final data left in the input register in the memory MEM-1 is written in the RAM. On the reading side, a reading dummy clock is generated in the memory MEM-2 by the decay of the write end signal and the data is read out from the RAM through the output register. Since the write end signal is formed and the memories are switched to be used, a delay circuit can be omitted and the circuit can be simplified. |
申请公布号 |
JPS6077237(A) |
申请公布日期 |
1985.05.01 |
申请号 |
JP19830185547 |
申请日期 |
1983.10.04 |
申请人 |
FUJITSU KK;NIPPON DENSHIN DENWA KOSHA |
发明人 |
MATSUDA KIICHI;HONMA TOSHIHIRO;HIRAOKA MAKOTO;NISHIZAWA YOSHIJI;TSUDA TOSHITAKA;KURODA HIDEO;TAKEGAWA NAOKI |
分类号 |
G06F13/38;G06F5/06;G06F5/16;G09G5/397;G09G5/399 |
主分类号 |
G06F13/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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