发明名称 DATA TRANSMISSION SYSTEM
摘要 PURPOSE:To reproduce a faithful restored signal by inhibiting the accumulation of sound data of new prescrived unit quantity to a buffer memory in case an idle area is not filled with said unit quantity when said sound data arrives. CONSTITUTION:An idle area monitor and calculation circuit 36 calculates the accumulating area of a buffer memory from a store address fed to the memory 32 from a serial/parallel converting circuit 31 shown by a counter circuit 33 and an extraction address fed to a compound processing circuit 34 from the memory 32 shown by a counter circuit 35. Then an idle area is calculated by comparing the extracted address with the memory capacity of the memory 32 which is set proviously. The circuit 36 receives an information showing that the new unit quantity of a compression signal s2 arraives from a transmission line 2 then compares the not-yet accumulated area with the unit quantity. Then the circuit 36 transmits a control signal c1 to the circuit 31 when the idle area is less than the unit quantity due to a fact that the arriving speed of the signal s2 is higher than the synthesized speed of a restored signal s3. Then it is inhibited to accumulate the signals s2 arriving newly to the memory 32.
申请公布号 JPS6076832(A) 申请公布日期 1985.05.01
申请号 JP19830185546 申请日期 1983.10.04
申请人 FUJITSU KK;NIPPON DENSHIN DENWA KOSHA 发明人 YASUI YUTAKA;YODA MASAAKI
分类号 H04B1/66;H04B14/04 主分类号 H04B1/66
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