| 摘要 |
PURPOSE:To obtain a decoder circuit which has a high working speed and not so much varies with the scale of a circuit by providing the circuits composed of the 1st Josephson elements having the 1st input signal lines corresponding to the number of bits of an input signal corresponding to the number of outputs of the decoder. CONSTITUTION:A DC bias current IBIAS is supplied to a decoder circuit using a Josephson element, and the IBIAS flows to a left branch LOOP1 for four circuits, respectively. With application of a set signal current Iset, QS1-QS4 are switched to change the current flowing to the LOOP1 to a branch LOOP2. Then the Iset is set at ''0'' and an address signal is supplied. Thus the current flows to an IA and An I-B, therefore QA1, QA2, QB2 and QB4 are switched respectively. Then the current flowing to L1, L2 and L4 are sent back to the LOOP1. Under such conditions, a start signal current Istart is supplies. Thus a Q03 is switched and the currents corresponding to A and -B flow to JS3, RS3 and LS3 respectively to obtain an output to be fed to the next stage. In this case, the JS3 is also switched and therefore the current of the JS3 is turned into a 1-shot pulse. Then the current so far flowing to a Q03 is sent back to the LOOP1, and reset to its original state. |
