发明名称 MOS TYPE SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent the lowering of ON withstanding voltage with the increase of an FET by forming contacts among source aluminum wirings and a semiconductor substrate or wells in all source diffusion regions. CONSTITUTION:Source diffusion substrate contacts 4 are formed so as to be uniformly distributed in source diffusion regions in order to prevent the lowering of ON withstanding voltage, and contacts 5 among source diffusion and source aluminum wirings are shaped near the contacts 4. Carriers injected into wells are collected efficiently to a semiconductor substrate in 4 and the source diffusion contacts, the rise of well potential is inhibited, and ON withstanding voltage is improved. Gate electrodes are made of silicon or aluminum. The titled integrated circuit can also be applied to an offset transistor and a self-alignment transistor.
申请公布号 JPS6076160(A) 申请公布日期 1985.04.30
申请号 JP19830184737 申请日期 1983.10.03
申请人 SUWA SEIKOSHA KK 发明人 SAKURAI YOUICHI
分类号 H01L21/8234;H01L23/522;H01L27/08;H01L27/088;H01L29/78 主分类号 H01L21/8234
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