| 摘要 |
PURPOSE:To reduce number of elements and power consumption of a digital arithmetic circuit comprising a logical circuit and a latch circuit by designing that a current of a current source flows to either the logical circuit or a common emitter of two transistors (TRs). CONSTITUTION:A TRQ3 and a clock signal source CL connected to its base controls whether a collector current of a Q31 flows to the logical circuit L1 or to Q1, Q2. When the collector current flows to the logical circuit L1, the logical circuit L1 is operated and two current outputs are given to emitters of the Q1, Q2. Then a carry signals C', C appear respectively at the collectors of the Q1, Q2. On the other hand, when the collector current flows to the common emitter of the Q1, Q2 via the Q3, since the collector and the base of the Q1, Q2 are connected together, they hold the carry signals C', C just before. Thus, the number of elements of the arithmetic circuit comprising the logical circuit and the latch circuit is decreased and the power consumption of an LSI produced by a bipolar IC manufacture process is halved. |
