| 摘要 |
PURPOSE:To filter the data having a short sampling cycle by cascading two unit groups in terms of an addition circuit and adding a compensating circuit which delays the input data. CONSTITUTION:Product/sum arithmetic circuits 21, 23 and 25 having taps to which odd-numbered coefficient data h1, h3 and h5 are supplied are cascaded in terms of an adder to form the 1st unit circuit group. While product/sum circuits 22 and 24 having taps to which even-numbered data h2 and h4 are supplied are also cascaded in terms of an adder to form the 2nd unit circuit group. Then the input of addition of the circuit 25 is set at 0, the output of the circuit 21 is used as an input of addition of the circuit 24. The input data supplied to the 1st unit circuit group is delayed via a correcting circuit 31 and then supplied to the 2nd unit circuit group. Then the data is extracted out of the circuit 22. Thus it is possible to form a digital filter by using product/sum circuits and then to filter the data having a short sampling cycle. |
