| 摘要 |
PURPOSE:To provide a broad phase variable width to the frequency of a transmission signal by combining plural kins of clocks different in frequency generated in a phase locked loop and applying logical processing to the combined result to obtain a timing signal having an optional relation of phase. CONSTITUTION:A reception signal fed to a terminal 1 is applied to an identifier 3 and a full-wave rectifier 7 via an equalizing amplifier 2. A rectified 7 signal is fed to a resonance circuit 8 for a transmission signal having a basic frequency (f), converted into a sinusoidal wave of frequency (f) and then fed to a comparator 10. The comparator 10 generates a clock signal C1 in synchronizing with the time of zero cross of the sinusoidal wave. The output of a VCO5 having an oscillating frequency nearly 2N times the frequency (f) is frequency-divided by 1/2N at a frequency divider 6 and goes to a clock signal C2. The signals C1 and C2 are subject to phase comparison 11, and its phase difference signal controls the frequency and phase of the VCO5 via an LPF12. A logical circuit 13 forms 2Npcs. of timing signals whose phases are shifted by 360 deg./2N by using the frequency-divided signal at the inside of the frequency divider 6, one of them is selected by using a signal from a terminal 14, and the identification timing is decided by applying the selected signal to the identifier 3. |
