发明名称 |
DUPLICATED CHANNEL CONTROL SYSTEM |
摘要 |
PURPOSE:To decrease amount of cables between a duplicated time division channel and a duplicated time division channel controller by providing a confounding circuit between duplicated time division channel controllers. CONSTITUTION:An order controlling a time division channel is transmitted from a call controller via an interprocessor bus 60 and fed to a common control section 30C via a selector 30B. The common control section 30C decodes the order, sets a value of flip-flops 30F, 30P and controls selectors 30H, 30Q. The next order is fed to other common control section 31C via an interprocessor bus confounding line 50 to set a vlaue of a flip-flop 31P. Since a desired channel control bus confounding pattern is designated by giving a value of the flip-flop of both the systems, even if a fault occurs in the channel control bus of one system, one or both time division channels are controlled. |
申请公布号 |
JPS6075198(A) |
申请公布日期 |
1985.04.27 |
申请号 |
JP19830183631 |
申请日期 |
1983.09.30 |
申请人 |
NIPPON DENKI KK;NIPPON DENSHIN DENWA KOSHA;OKI DENKI KOGYO KK;HITACHI SEISAKUSHO KK;FUJITSU KK |
发明人 |
MATSUMOTO TAKASHI;SANBE TAKESHI;TAKAHASHI HIDEO;TOKUNAGA KAORU;SASAKI YUUZOU |
分类号 |
H04Q11/04;(IPC1-7):H04Q11/04 |
主分类号 |
H04Q11/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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