| 摘要 |
PURPOSE:To enable to have equal plane areas on a chip, and to remove the phenomenon of latch-up action a structural defect of a CMOS device by a method wherein a logic element is prepared on a wafer in three-dimensions. CONSTITUTION:The gate 1 of an N-MOST is connected to the gate 20 of a P- MOST by means of a poly Si wiring 21 and turns to the input of this CMOS inverter. When a positive voltage is impressed on the wiring serving as the input, with VCC as the positive potential; the gate poly Si 1 of the N-MOS connected to the wiring turns to a positive voltage, and the gate poly Si 20 of the P-MOST to a positive voltage. The turning of the gate poly Si of the N-MOST to a positive voltage induces electrons in the neighborhood of the surface of a P<-> substrate 6 contacting the gate oxide film 2 of a P<-> region sandwiched between P<-> diffused layers 4 and 5 placed between N<+> diffused layers 4 and 5. As a result, the channel activates, and the N-MOST turns ON. At the same time, when the gate poly Si of the P-MOST turns to a positive voltage, the P-channel does not activate and turns OFF. |
