发明名称 |
CONTROL METHOD FOR I/O DEVICES |
摘要 |
The data transmission is accomplished by transfer from a main memory(1) to an I/O controller(51) through a channel controller(3) which provides responsing signal to the I/O controller in normal state. The provision of the responsing signal stops by error detection of channel controller and the I/O controller detects the absence of the responsing signal through a time interval supervising circuit positioned on a bus supervising circuit. Then, the faulty address and content of an I/O device(61) are reported to a CPU(2) through the channel controller.
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申请公布号 |
KR850000561(B1) |
申请公布日期 |
1985.04.26 |
申请号 |
KR19790003174 |
申请日期 |
1979.09.14 |
申请人 |
FUJITSU FANUC LTD. |
发明人 |
MARUOKA, MINEKAZU;HIRODANI, DAZUSHI |
分类号 |
G06F11/00;G06F13/12;(IPC1-7):G06F13/12 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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