发明名称 HIGH SPEED MEMORY INTEGRATED CIRCUIT
摘要 PURPOSE:To attain stable read-write by providing a delay circuit, reset/set flip- flop circuit and a read/write control circuit, and using the pulse edge of an R/W control pulse, and generating a proper pulse suitable for the R/W control at the inside. CONSTITUTION:R/W control signals are inputted from a terminal 20; one is inputted to a reset terminal 22 of the reset/set flip-flop (RS-F/F) circuit 25 via a delay circuit 21, and the other is inputted to a set terminal 26 of the RS-F/F25 not through the delay circuit and they are outputted from terminals 23 and 24 as true logic signal and complementary logic signal. Since a voltage corresponding to an input threshold voltage VTH of the RS-F/F circuit 25 is applied at a point P at a set input terminal 26 of the RS-F/F circuit 25, the voltage waveform set by the RS-F/F circuit 25 rises at the point P and falls down at a point Q. Since the pulse width depends on a delay time (d) of the delay circuit 21, the width is selected optionally by adjusting the delay time.
申请公布号 JPS6074195(A) 申请公布日期 1985.04.26
申请号 JP19830181099 申请日期 1983.09.29
申请人 NIPPON DENKI KK 发明人 TAKAHASHI KAZUKIYO
分类号 G11C11/417;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/417
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