发明名称 CONTROL CIRCUIT OF TIMER OUTPUT
摘要 <p>PURPOSE:To prevent the malfunction of a peripheral device, by inhibiting the propagation of an unnecessary signal generated and outputted before initialization from an LSI for timer control until the initialization is completed. CONSTITUTION:An FF14 and gate circuit 15 are added to the titled circuit. When the power is supplied to this system, a power-on clear signal is generated, and a microprocessor 11 and various logics are initialized based on the signal. When the FF14 is initialized under this conditon, the output of the FF14 is energizes the gate circuit 15 through a line 105 so as to inhibit sending out of a signal generated and outputted from an LSI12 for timer control. Since the propagation of an unnecessary signal from the LSI12 is inhibited, the malfunction of a peripheral device is prevented.</p>
申请公布号 JPS6073722(A) 申请公布日期 1985.04.25
申请号 JP19830180540 申请日期 1983.09.30
申请人 TOSHIBA KK 发明人 SASAKI TERUO
分类号 G06F1/24;G04G15/00;G06F1/04 主分类号 G06F1/24
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