| 摘要 |
PURPOSE:To simplify circuit configuration of a demodulating section by binary encoding a binary information series, modulating and transmitting it, and after multiplying modulated wave in receiving side, reproducing the series of binary information by the action of a 1 bit delay sine detector. CONSTITUTION:A binary information series (an) inputted from a terminal 1 is converted to a binary series (bn) in a polybinary precoder 2. This value bn is given by a sum that makes the value of 2L-2 past data and the value of present an divisors, and polybinary encoding suitable to obtain phase continuous FSK modulated wave is performed. A modulating section 4 generates phase continuous FSK modulated wave having maximum value of L-1/2 modulation index of (h) by this pulse train. This modulated wave is sent to a transmitting section 5 and transmitted from an antenna. On the other hand, the receiving side receives 6 a receiving signal and after multiplying the modulated wave by a (L-1/2)/h multiplying circuit 7, binary discriminates 9 by the action of a 1 bit delay sine detector 8 and reproduces original series of binary information. |
