发明名称 OPERATION PROCESSOR
摘要 PURPOSE:To shorten an instruction executing time by providing two circuits for both addition and subtraction use, on a circuit connected to a carry-in input, a carry-out output and a data output of a decimal adder. CONSTITUTION:A decimal adding part 1 is constituted of a decimal adder 3, a data holding means 6, a data selecting means 7, etc. Codes of the first and the second operands which are inputted are held by a holding means 2, and sent to the selecting means 7. The adder 3 has two data inputs, has a function for adding and subtracting both of them, and also has a carry-in input and a carry- out output for processing an operand being larger than the number of characters which can be processed at the same time by dividing it into several times. A carry-out holding means 5 adds and subtracts an output of the adder 3 and holds it separately, sends it to a carry-in data selecting circuit 4, and selects it to match an operating mode. Each data output which has been held is selected and outputted by a code of said operand, etc. by the data selecting means 7.
申请公布号 JPS6072025(A) 申请公布日期 1985.04.24
申请号 JP19830181543 申请日期 1983.09.28
申请人 NIPPON DENKI KK 发明人 SHIMODA WATARU
分类号 G06F7/494;G06F7/495;G06F7/50;G06F7/507 主分类号 G06F7/494
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