| 摘要 |
<p>A shift register having a simple circuit structure and used, for example, in a dynamic RAM device for a refresh operation. The shift register comprises a plurality of circuit stages mutually connected in cascade. Each of the circuit stages comprises: a first transistor (Q4) for a transfer gate which is turned on and off by a first clock signal (00) and to which is input the output signal (OUT) of the previous circuit stage; a second transistor (Q5) whose gate electrode is connected to the output of the first transistor, whose drain or source electrode receives a second clock signal (01) having a different phase from the first clock signal, and whose source or drain electrode outputs an output signal; and a reset means (Q6, C2) for rendering the input portion of the first transistor to a reset condition on the basis of the output signal, thereby sequentially transmitting data through each circuit stage.</p> |
