| 摘要 |
PURPOSE:To make the jitter of a clock zero when no frequency lag occurs, by treating the phase of digital signals in such a way that when the difference between input and output phases is within one pulse of a clock pulse the phases are treated as under a synchronous condition and no phase correcting signal is outputted. CONSTITUTION:A clock Q in which the phase is delayed is obtained by dividing 3 the output of an oscillator 5 into N parts and using a frequency which is almost same as the frequency of an input signal as an output clock P, and then, shifting the clock P by one pulse after giving to a shift register 4. Phases of the clocks P and Q are compared 1 with each other. An up-down counter 2 counts the number of signals which are under a led and delayed conditions only in accordance with the compared result and, when the counted number reaches a previously set value, phase correction is performed. As a result, when the difference between input and output phases is within the one pulse of the clock pulse, they are treated as under a synchronous condition and no phase correcting signals is outputted. |
