| 摘要 |
An information processing system using a virtual addressing for paging, including a main memory, a memory controller, a central processing unit for processing information and accessing the memory controller with a virtual address, an input/output controller for interfacing input/output devices with the memory controller and the central processing unit, a common bus for interconnecting the memory controller, the central processing unit and the input/output controller with each other. The memory controller includes a translator for translating the virtual address into a real address, whereby the virtual address is available for addressing the main memory after being translated into the real address.
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