| 摘要 |
An error correction device for digital data storage and transfer systems wherein data are transferred over a plurality of channels. Synchronously with the transfer of a group of data bits, a coding device forms a first correction bit for a first correction channel and a second correction bit for a second correction channel. The first correction bit is formed on the basis of a second group of data bits, the second correction bits being formed on the basis of a third group of data bits. Each data channel supplies the data of two sub-groups of data bits for this purpose. The delay operator having a length of one bit cell being represented by D, a series of directly successive bits can be represented by a polynomial in D: x0.D0+x1.D1+x2.D2+ . . ., in which xj (j =0, 1 . . .) represents the bit value. The quotient of the polynomials relating to the two sub-groups of a data channel is different for each data channel in order to enable correction of an arbitrary error pattern in a single data channel. When the data bits and correction bits are received, a first and a second error elimination bit are calculated from the extracted data bits by using the same algorithm. Comparison of first/second correction/elimination bit produces two error detection bits. When a given number of successive error detection bits do not indicate a discrepancy, the transfer medium is error-free. When a given configuration of discrepancies is detected, a correction vector is formed which indicates, after storage, the channel containing an error, while further error detection bits indicate the error pattern which can thus be corrected. |
