| 摘要 |
PURPOSE:To miniaturize a counter circuit by designing a parity check circuit, a parity pre-detect circuit and a decode circuit with read only memories. CONSTITUTION:Output lines 101, 102-108 of a counter 110 represent binary values, in which the line 101 represents the most significant bit and the line 108 indicates the least significant bit. Whether the counter 110 increments or decrements is designated in advance by an up/down command 202. An initial set command 204 sets the counter 110 and an expected parity storage circuit 160. Thus, a read only memory 130 computes and outputs a parity error 1303 and the next expected parity bit 1304 depending on the values of the output lines 101-108 and 1601. When a count clock 203 is incoming, the counter 110 counts the clock and the storage circuit 160 stores the next expected parity bit 1304 and a parity error storage circuit 150 stores the parity error 1303 respectively. |
