| 摘要 |
PURPOSE:To speed up DELTA function operation while maintaining precision by outputting the multiplication result between signal-precision data and double precision data with double precision as the result of operation which is performed by a pipeline multiplier. CONSTITUTION:Data having signal precision and double precision are inputted to inputs 2-1 and 2-2 respectively. Exponent parts of the signal precision and double precision data are set in registers 103 and 104 at the 1st stage 2 of the multiplier. Mantissa parts are set in registers 116 and 117. The exponent parts are summed up by an adder 105 and set in a register 107 at the 2nd stage 3. The mantissa parts are multiplied by a multiplier 118 and set in a register 119. The contents are transferred to a register 108 as they are and the multiplication result of the mantissa parts are added by an adder 120 by using the shift contents of the output at the 3rd stage 4. A bit correction control circuit 126 makes bit corrections at the 4th stage 5 when necessary and the contents of the registers 108, 113, and 121 are outputted by an output control circuit 125. |
