| 摘要 |
PURPOSE:To simplify the hardware of an overflow detecting system, by detecting an overflow in such a way that the 1st data having fixed values in high-order values and variable values in low-order values and the 2nd data having variable values only are added to each other and the 1st data are compared with the fixed value of the added output and, at the same time, outputting the fixed values of the 1st data and variable values of the added output in a chain. CONSTITUTION:The 1st data composed of a fixed-value section and low-order variable-value section and the 2nd data composed only of a variable-value section are respectively stored in input registers 2 and 3 and they are added to each other over the entire width by means of an adder 5. Switches 6, 7, 8, and 9 selects desired bit outputs from inputs in accordance with the attribute (bit numbers of the fixed-value and variable-value sections) of the 1st data. A comparator 10 compares the fixed value section of the 1st data with the fixed-value section of the added result and detects an overflow when they do not coincide with each other. An output register 4 exclusively adds the fixed- value section of the 1st data and variable-value section of the added result to each other and forms a chain, and thus, obtains a regular arithmetic result S. |
