发明名称 TIMING ADJUSTING METHOD
摘要 PURPOSE:To eliminate the need for manual timing adjusting operation and reduce the man-hour of timing adjustment by reading delay phase data out of a semiconductor memory through a data selector, and connecting plural delay circuits selectively. CONSTITUTION:The data selector 7 is controlled with the control signal of an up/down counter 8 to send out its output signal to a phase comparing circuit 9, and the phase difference from the input signal to a circuit 6 to be adjusted is detected to put the up/down counter 8 in up/down counting operation repeatedly up to a target value. Then, the up/down counter 8 stops at the target value, and a phase comparing circuit 9 sends out a write signal to an ROM writer 10 to write the counted value in a semiconductor memory 11. The data selector 7 reads delay phase data out of a semiconductor memory circuit 12 into which the semiconductor memory 11 is inserted to connect selectively delay circuit 21...2n in the circuit 6 to be adjusted, thereby outputting a specific phase timing signal.
申请公布号 JPS6069722(A) 申请公布日期 1985.04.20
申请号 JP19830177262 申请日期 1983.09.26
申请人 FUJITSU KK 发明人 NARITA YOSHIAKI
分类号 H03K5/135;G04F10/00;G06F1/06;G06F1/10;G11C11/407;H04L7/00 主分类号 H03K5/135
代理机构 代理人
主权项
地址