| 摘要 |
PURPOSE:To avoid timewise space between both transmitted packets by transmitting a packet from one of two transmission packet storage means connected in parallel and transmitting successively a packet from the other storage means. CONSTITUTION:A CPU1 contains special packet information stored in a special packet storage area 3b in a storage device 3 in a transmission register 6 and sets the length of a special packet to a length counter 13. When transmission data is generated and data are arranged in a data packet storage area 3a, data packet information is contained in a transmission register 5 and the length is set to a length counter 12. The CPU1 outputs a transmission start signal 20 to a start circuit 8 to start a transmitter 4, an output of a register 5 is selected (7) by a signal of a register changeover circuit 14, the result is transmitted to a transmission line 15 while being subjected to P/S conversion 11. When a data packet transmission end signal is transmitted from the counter 12, the CPU1 outputs (7) the special packet information of the register 6 and transmits it to a transmission line 15 while being subjected to P/S conversion 11. |
