| 摘要 |
PURPOSE:To detect a malfunction of a control logical circuit by setting a parity of each register to an odd or even parity, whenever a control signal to the first register is generated, in plural registers, and executing an odd or even parity check. CONSTITUTION:In case no set signal of a gate register 5 and a parity register 6 is issued due to a malfunction of a control logical circuit 1, the register 5 and 6 remain holding a value which is stored immediately before that time, and an odd parity is stored in the register 6. In this case, due to the malfunction of the circuit, a data register signal on a signal line 104 does not become '1', but an instruction code register set signal on a signal line 103 becomes '1', and the contents of a counter 4 are updated and become '1'. Also, since an even parity indicating signal on a signal line 109 is '1', an output of the register 6 is inverted by an exclusive OR circuit 7, and brought to an even parity check. However, since the register signal on the signal line 104 does not become '1', the output of the register 6 becomes and odd parity which is stored immediately before that time. |
