| 摘要 |
<p>Disclosed is a circuit which provides a double clocking latch during testing of the circuit to prevent race or flushing of the scan rings from occuring during the test mode and yet can be operated to capture and hold output data during the operation mode with stable data inputs. The preferred embodiment is a programmable latching circuit (transistors 41 to 52) comprising a double ended cross coupled circuit having first (47, 48) and second (44, 45) programmable legs and a third non-programmable leg (49, 50) with the first programmable leg (47, 48) cross coupled to the third leg (49, 50) and the second programmable leg (44, 45) being switchably cross coupled to the third leg (49, 50).</p> |
