发明名称 Digital processor with floating point multiplier and adder suitable for digital signal processing
摘要 A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor is capable of executing data input/output operations with an external circuit in the data format of the fixed point representation and of performing internal operations in the floating point representation format. Further, conversion of an operational result from fixed point representation to floating point representation, and vice versa, can be performed internally in accordance with program instruction.
申请公布号 US4511990(A) 申请公布日期 1985.04.16
申请号 US19810311680 申请日期 1981.10.15
申请人 HITACHI, LTD.;HITACHI DENSHI KABUSHIKI KAISHA 发明人 HAGIWARA, YOSHIMUNE;SUGIYAMA, SHIZUO;MAEDA, NARIMICHI;YUMOTO, OSAMU;AKAZAWA, TAKASHI;KOBAYASHI, MASAHITO;KITA, YASUHIRO;KITA, YUZO
分类号 G06F7/00;G06F5/01;G06F7/50;G06F7/57;G06F7/76;G06F17/10;(IPC1-7):G06F7/48 主分类号 G06F7/00
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