发明名称 MOS INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To enable to shorten channel length, and to enhance the degree of integration of an MOS integrated circuit device by a method wherein P-channel MOSFETs are constructed being integrated on a semiconductor substrate. CONSTITUTION:P<+> type diffusion layers 12, 13, a gate oxide film 14 and a gate electrode 15 are formed on the surface of an N type Si substrate 11 to form a P-channel MOSFET of channel length LP <=0.4mum. At the P-channel MOSFET holding holes as carriers, generation of hot electrons itself becomes extremely small, and when channel length is 0.4mum or less and even when at the degree of 0.1mum, a trapping phenomenon into the gate oxide film of hot electrons is not generated.
申请公布号 JPS6066472(A) 申请公布日期 1985.04.16
申请号 JP19830175014 申请日期 1983.09.21
申请人 SUWA SEIKOSHA KK 发明人 IWAMATSU SEIICHI
分类号 H01L29/78;(IPC1-7):H01L29/78 主分类号 H01L29/78
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