| 摘要 |
PURPOSE:To reduce the hardware quantity at an interface section by accommodating a CPU and an input/output device in a high-speed optical loop and a channel system device and a signal processor to a low-speed optical loop respectively and controlling the information by a communication controller between the devices. CONSTITUTION:Plural processors CP1-CPn, a data channel device DCH, and inter-device communication controller IECC30 performing communication control between loop control and other loop device are connected to the high-speed optical loop 10. A network NW, a signal processor STE and the IECC30 are connected to the low-speed optical cable 20 and input/output information is transmitted in the form of bit serial in both the optical loops. The IECC30 consists of an optoelectric converting section O/E, an electrooptic converting section E/O and a control section connected to the electric side, a common memory device CM and a supervisory test equipment STE are connected in the form of matrix and the information is transmitted/received through the cross point control by the control section. |
