发明名称 SIGNAL DECIDING CIRCUIT
摘要 PURPOSE:To decide plural conditions at a time and with a simple circuit by using a memory which has an address input of the same number of bits as those of an input signal and delivers the data of >=1 bit. CONSTITUTION:An input signal 10 contains 4 bits, and a memory 1 has 16 addresses (=2<4>) with constitution of (16 addresses X 3 bits). For instance, the signal 10 has a bit pattern of 1001. In such a case, a deciding signal 11 is set at 0. While a deciding signal 12 is set at 1 when the signal 10 has bit patterns of 0000, 0010 and 1100. The signal 12 is set at 0 with other bit patterns. In addition, a deciding signal 13 is set at 1 when the bit patterns of the signal 10 are included within a range of 0010-1000. Otherwise, the signal 13 is set at 0. If these working conditions are set previously, the memory 1 uses the signal 10 as an address and delivers the contents of bits 1-3 in the form of deciding signals 11-13.
申请公布号 JPS6065332(A) 申请公布日期 1985.04.15
申请号 JP19830172677 申请日期 1983.09.19
申请人 ANDOU DENKI KK 发明人 ISHIKURA ISAO;SUZUKI NORIYUKI
分类号 H04L13/18;G01R13/28;G06F7/02;G06F7/04 主分类号 H04L13/18
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