| 摘要 |
PURPOSE:To obtain a CMOS adapted for high acceleration by reducing a drain capacity of a P-channel and N-channel transistors. CONSTITUTION:The structure of a CMOS element structure uses a high resistance N type substrate 201 of 5X10<-3> or lower of N type impurity density, boron ions are implanted as P type impurity, thereby forming a Pwe11202 of 3-10mum in the degree of 1 to 10X10<14>cm<-3> degree of impurity density by a heat treatment. Boron ions are implanted to the Pwe11 region and phoshorus ions are implanted to a P channel region, a heat treament is performed, and a P type diffused layer 206 and N type diffused layer 207 are formed to become 0.5- 1.5mum of depth, 1-6X10<16>cm<-3> of substrate surface density, 1-3X10<13>cm<-3> of N type substrate region respectively. According to this structure, a drain capacity is reduced to approx. 30% of the conventional method, and the surface density is not almost varied as compared with the conventional method. In other words, the drain capacity is largely reduced, and the structure is adapted for high speed operation. |
