发明名称 SWITCHED CAPACITOR MULTIPLIER CIRCUIT
摘要 PURPOSE:To obtain a high-precision arithmetic result by eliminating an error due to a feedthrough and an error due to the offset of an amplifier by a combinational logical circuit which generates driving signals for the 1st - the 4th analog switches. CONSTITUTION:When data applied to a data input terminal 2 is ''+1'', switches 8-5 and 8-8 are turned on to fetch an analog signal applied to an input terminal 1 in a capacitor 10 temporarily. Then switches 8-6 and 8-7 are turned on to charge an output capacitor 11. When the data is ''-1'', the switches 8-6 and 8-7 are turned on directly to charge the output capacitor 11 through the input capacitor 10. When the data is ''0'', the switches 8-6 and 8-8 are turned on firstly to reset the charge in the input capacitor 10, and then the switches 8-6 and 8-7 are turned on to perform transfer to the output capacitor 11.
申请公布号 JPS6063683(A) 申请公布日期 1985.04.12
申请号 JP19830170880 申请日期 1983.09.16
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 TAKATORI HIROSHI;SUZUKI TOSHIROU;KANAYAMA MASABUMI
分类号 G06G7/16;G06J1/00 主分类号 G06G7/16
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