| 摘要 |
PURPOSE:To prevent a master processor from disabling due to a fault occurring to a slave processor by releasing the master processor from a wait state without fail when the master processor is kept in the wait state continuously for longer than a specified time. CONSTITUTION:The master processor 1 is provided with a monitor timer mechanism 11, and salve processors 2 and 3 are provided with NORDY control circuits 22 and 23. The monitor timer mechanism 11 turns on automatically a monitor signal line 12 a preset time later. Once the monitor signal line 12 is turned on, the NORDY control circuits 22 and 32 turns off an NORDY signal line forcibly to release the master processor from a wait state. |
