| 摘要 |
A decoder for converting a linear p.c.m. input at a pulse density modulated (p.d.m.) sampling rate to a sigma-delta type p.d.m. binary stream, which can be demodulated by a simple R.C. filter, or otherwise, provides an analogue output as in a digital-to-analogue converter if required. The decoder basically comprises first and second recursive filters (F', G'), the output of the first (F') being applied to the input of the second (G'), which in turn outputs to digital comparator (13). Depending on the output of the comparator, a signal Q' has one of two values and is applied wholly or proportionally to the first recursive filter (F') and proportionally (as P') to the second recursive filter (G'). Each recursive filter comprises a respective multiplier (21, 22) and a respective storage register (11, 12) clocked at the same clock rate (fc), and with an input comprised by a respective adder (9, 10). Other circuit configurations (Figs. 3 to 7) conforming to the same simulation formulae as Fig. 8 are described. <IMAGE> |
