发明名称 SEMICONDUCTOR MEMORY REDUNDANCY CIRCUIT
摘要 A redundancy circuit for a semiconductor memory includes an ordinary decoder which selects a desired memory section in an ordinary memory, and a spare decoder which selects a desired memory section in a spare memory. The ordinary decoder includes a plurality of output inverters, each of which is connected to the corresponding ordinary memory section via an ordinary memory word line. A fuse is disposed in the ordinary memory word line so that the output inverter is disconnected from the ordinary memory section when some defects are included in the corresponding ordinary memory section. A pull-down transistor is connected to the ordinary memory word line in order to permanently maintain the ordinary memory word line at the logic low when the corresponding fuse is burned out. <IMAGE>
申请公布号 GB8505764(D0) 申请公布日期 1985.04.11
申请号 GB19850005764 申请日期 1985.03.06
申请人 SHARP KK 发明人
分类号 G11C29/00;G11C29/04;H01L27/10 主分类号 G11C29/00
代理机构 代理人
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