| 摘要 |
PURPOSE:To easily obtain a power CMOSIC using a vertical type power MOS by a method wherein N type and P type semiconductors are provided on an insulated substrate, and an N-channel vertical type power MOS and a P-channel vertical type power MOS are provided thereon respectively. CONSTITUTION:A P-region 13 is selectively provided on the N type Si layer 12 on sapphire 7, and another N-region 14 and a P-region 15 are formed by removing the boundary part by etching. Subsequently, a P-channel vertical type MOS10 is formed on an N-region 8 and an N-channel vertical type MOS11 is formed on a P-region 9 by performing the publicly known method of manufacture. Also, when the region 8 and the P-region 9 are isolated by performing a selective oxidization using an insulator, a flat surface is obtained and the disconnection of a wiring can be prevented, thereby enabling to easily obtain a power CMOS whereon a vertical type element is used. |
