| 摘要 |
<p>A latching output buffer (11) has an amplifier (50) for providing output signals on first and second nodes (23, 24) in response to complementary data signals (D, D) when an equalization pulse (EQ) is not present. When the equalization pulse (EQ) is present, a latch (40) sustains the output signals on the first and second nodes (23, 24), and the amplifier (50) is not operational. When the equalization pulse (50) is not present, the latch (40) is not operational.</p> |
