| 摘要 |
PURPOSE:To increase the operation speed of a circuit by transferring the variation state of data inputted to a master part partially to a slave part preliminarily before an input signal is inputted, and maintaining the hold state of the slave part. CONSTITUTION:The master part 10 is activated with the clock signal phi, and data Di is transmitted in the order of transistor (TR) Q4, Q5, Q6, Q7, Q3, and Q2 and transferred to the slave part 20 through points A and B. The held data of the slave part 20 is updated and led out as outputs D01 and D02. Schottky diodes D1 and D2 are connected between the collectors of TRs Q2 and Q3 and the collectors of TRs Q4 and Q5 to make a shift in transfer output level. The variation state of the data Di of the master part 10 is transferred partially to the slave part 20 preliminarily before the signal phi is inputted, and the level of the preliminarily transferred variation state is so set as not to invert the hold state of the slave part 20. Thus, the operation speed of the slave part 20. Thus, the operation speed of the circuit is improved. |
