| 摘要 |
PURPOSE:To prevent reduction of the processing speed of a data processor by performing a data refresh action of a memory block at the other side in the same memory cycle of the other memory block while an access is given to either one of even and odd memory blocks. CONSTITUTION:The least significant bit address 35 among addresses of an address bus 13 is set at level ''0'', and a row address strobe signal 19 given from a timing generating circuit 15 is lowered down to level ''0''. Under such conditions, memory blocks 24 and 25 of the ven side receive accesses to a request given from a processor 11 and perform the transfer of data with a data bus 14 via data buses 29 and 30. For memory blocks 26 and 27 of the odd side, an address which is designated by a refresh address address 75 is refreshed since the supply is inhibited for a column address strobe signal 39 by an NAND gate 34. When the address 35 is set at level ''1'', the data receives an access at blocks 26 and 27. Then the data is refreshed at blocks 24 and 25. |
