| 摘要 |
PURPOSE:To decrease the reading time of data by using plural memory parts having desired memory capacity and supplying different read addresses simultaneously to these memory parts. CONSTITUTION:For writing of data to memory parts 1a, 1b and 1n, selectors 7a, 7b and 7n are first controlled to the write address selecting side via a selection control line 10. Then the write address, the write data and an enable signal are supplied simultaneously to the parts 1a, 1b and 1n via a write address line 8, selectors 7a, 7b and 7n and address lines 11a, 11b and 11n, a write data line 4 and an enable control line 3, respectively. Furthermore the write signal is supplied to the parts 1a, 1b and 1n at a time via a write control line 6. Therefore the data is written to the same address of (n) units of memory parts at a time just by a writing action. While the data is read out by reading first selectors 7a, 7b and 7n via the control line 10 and controlling these selectors to the address selecting side. |
