发明名称 MEMORY CIRCUIT
摘要 A fault tolerant memory system includes redundant rows which may be permanently substituted for defective rows according to priority. The system also includes means for substituting a redundant row for a defective redundant row previously connected in circuit.
申请公布号 JPS6062000(A) 申请公布日期 1985.04.09
申请号 JP19840086055 申请日期 1984.04.26
申请人 RCA CORP 发明人 IHOORU TARASU WASHIIKU
分类号 G11C29/00;G11C29/04 主分类号 G11C29/00
代理机构 代理人
主权项
地址