| 摘要 |
PURPOSE:To realize a highly accurate detection with the minimum delay time by managing the delay in and the accuracy of the detection independently of each other. CONSTITUTION:Output signals from a pulse generator are inputted into a counter 4 through a waveform shaping circuit 3 to count. The counter 4 is set by a counter synchronous signal from a control signal generation circuit 6 at a fixed time interval. A data latch 5 latches counts immediately before the resetting of the counter 4. A CPU1 reads pulse counts latched with the data latch 5 and executes the computation for the detection of speed according to a specified algorism. |
