| 摘要 |
PURPOSE:To speed up data cycle time by writing plural input data in plural memories simultaneously with continuous reading from plural memory cells without overlap. CONSTITUTION:A data input buffer 17 is controlled by a write control clock WE' activated in one cycle time of a reference clock CAS' through a write timing circuit 16 or the like and plural input data are written in plural memory cells 12. These stored contents are stored in a corresponding data output buffer 20 through a data transfer gate 19 controlled by a transfer clock DT' activated in one cycle time delayed from the clock CAS'. The buffer 20 is controlled by reading clock SO', S1 successively activated in one cycle time of the clock DT' synchronously with the DT' and the stored contents are successively read out without overlap, so that the data cycle time is speeded up. |
