| 摘要 |
PURPOSE:To prevent abnormal synchronism from being established by allowing a clock width supervising circuit to supervise a clock width of a transmission/ reception clock, and deciding it as synchronism abnormal until a normal clock is received over regulated time if an abnormal clock width different from the regulated time width is detected. CONSTITUTION:A comparator circuit 23 decides whether the clock width is <=90% or not. When the clock width is >=110%, a report signal is transmitted on a signal line 24 and when the width is <=90%, the report signal is transmitted to a signal line 25. When it is significant that the width is >=110% or <=90%, a signal representing abnormity is held in a clock abnormity holding circuit 26 in the timing of a clock signal CP1, and the abnormity of synchronism is reported by a signal on a signal line 27. If the abnormal clock is not detected within the regulated time, a reset signal is outputted to a signal line from a timer 28 to reset the clock abnormity holding circuit 26 thereby informing that the establishment of synchronism is possible. |
