| 摘要 |
PURPOSE:To obtain a bus.interface eliminating an address coincidence discriminating circuit, a timing circuit and a gate circuit by forming buses in serial and also not transmitting address information. CONSTITUTION:A bus controller 4 synchronizes an output data signal 22 to a clock signal 20 and outputs the result. A shift register group 50 is connected serially the same as that at the input side and shifted sequentially by the clock signal 20. When a data is shifted to a shift register 50 placed remotest from the bus controller 4, a set signal 24 is outputted. A value of each shift register 50 is stored in a register 51 of each process output device 3 by using the set signal. In order to ensure the reliability of data, a parity bit is transferred by including a transfer data, and parity check 55 is executed in storing the data to the register 51, the data is suppressed by an AND gate 56 and not stored at error detection. The processing above is performed cyclicly. |
