发明名称 PLL SYNTHESIZER RECEIVER
摘要 PURPOSE:To decrease the capacity of a preset memory by using a binary code representing a channel number as a channel data stored in the preset memory so as to reduce the number of bits. CONSTITUTION:A receiver is constituted of a specific value data generating means 10 storing a binary code representing a channel number as a channel data and also generating a binary code representing a prescribed specific value data to a preset memory 8, and an operating device 11 adding or subtracting the said specific value data and the channel data read from the preset memory 8 and supplying the result of operation to a programmable frequency divider 7 as a frequency dividing number. Through the constitution above, the channel number is given sequentially in a hexadecimal number from a lower limit frequency to an upper limit frequency of each broadcast channel of an FM band. The number is binary-coded and the binary code is stored in the preset memory 8 in place of the frequency division number. Thus, 8-bit is enough for the code and the bits are reduced by 2-bits in comparison with a conventional receiver.
申请公布号 JPS6058711(A) 申请公布日期 1985.04.04
申请号 JP19830167049 申请日期 1983.09.09
申请人 SANYO DENKI KK;TOKYO SANYO DENKI KK 发明人 ISHIMURA SHIZUKA
分类号 H03J5/00;H03J5/02 主分类号 H03J5/00
代理机构 代理人
主权项
地址