| 摘要 |
PURPOSE:To improve characteristics of a logic element securing tension resistance of a high tension resisting element by making the thickness of a semiconductor layer for a logic element forming region thinner and the thickness of a semiconductor layer for a high tension resisting element forming region thicker when an IC provided with the high tension resisting element and the logic element on the same semiconductor substrate is formed. CONSTITUTION:In a part of a p<-> type Si substrate 10, a recessed portion 20 of truncated pyramid shape, a region a1, is provided. In the region a1 and the adjacent regions a2 and a3, an n<+> type buried region 14 is formed by diffusion respectively. Then, on all the surface, an n<-> type layer 12 is grown epitaxially, a recessed portion 22 is provided on the surface corresponding to the region a3 where the thickness of the layer 12 is made thinner and the layer 12 is separated to an island state including the region 14 using a p type region 30. Later, a p type region 32 and a n<+> type region 40 for connecting to a collector in the region a1, the p type region 32 in the region a2 and the p type region 32 in the region a3 is diffused respectively. The region a1 is used for a n-p-n type bipolar transistor for high tension resisting linear, the region a2 is used is used for a normal n-p-n type element and the region a3 is used for an I<2>L element respectively. |
