| 摘要 |
A vector data processing system includes at least an A-access pipeline (27) and a B-access pipeline (28) between a main storage unit (4) and vector registers (21). Associated with the A-access pipeline (27) are a write port (WA) and a read port (RA) selectively connected to the vector registers (21). Associated with the B-access pipeline (28) are a write port (WB) and a read port (RB) selectively connected to the vector registers (21). An additional read port (IA) is linked between the read port (RB) of the B-access pipeline (28) and the address input side of the A-access pipeline (27). When an indirect address load/store instruction is carried out for the A-access pipeline (27), an indirect address is generated from the vector registers (21) via the read port (RB) of the B-access pipeline (28) and the additional read port (IA). |
