发明名称 Multiple port pipelined processor.
摘要 <p>A horizontal computation device includes a multi-ported random access memory in combination with independent pipelined memoryless function modules. The device is operative to implement a class of algorithms involving a high ratio of arithmetic computation to control complexity and good locality of data reference. The invention meets the criterion of a horizontal computation machine without undue complexity, that is, the invention provides a structure wherein a delay element capable of arbitrary delay can be allocated between every resource or function output and every resource or function input. The structure is a parallel input, parallel output random access memory having a plurality of dedicated serial buffered input ports and dedicated serial buffered output ports. The buffered ports are operative to provide transient storage in independent pipelines and parallel input and output to addressed locations of the random access memory. The invention also encompasses a program compilation technique and a multiple address bus primitive cell for a dynamic random access memory.</p>
申请公布号 EP0136218(A2) 申请公布日期 1985.04.03
申请号 EP19840401713 申请日期 1984.08.24
申请人 FAIRCHILD CAMERA & INSTRUMENT CORPORATION 发明人 LYON, RICHARD F.
分类号 G06F12/04;G06F15/16;G06F15/80;(IPC1-7):G06F15/06 主分类号 G06F12/04
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